1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to pad arrangements for reducing bonding failures and signal skew.
2. Discussion of the Related Art
As semiconductor manufacturing processes have improved, design rules have been reduced to allow for smaller and/or higher density semiconductor devices. However, for semiconductor devices having a large number of pads, the pad pitch limit, or pad-to-pad design rule, may define the minimum size.
FIGS. 1A to 1C are views of representative pad arrangements that are used on conventional semiconductor devices. FIG. 1A illustrates pads 98 arranged in a single row on a chip 100, FIG. 1B illustrates pads 98 arranged in two rows on a chip 100 and FIG. 1C illustrates pads 98 arranged around the periphery of a chip 100. FIG. 2 illustrates a conventional configuration of bonding wires 104 used to connect two rows of bond pads to the corresponding portions of a lead frame 102. As reflected in FIG. 2, the separation between the bonding wires 104 used to connect pads 1-3, 6-11 and 14-16 to the corresponding portions of the lead frame 102 is reduced, increasing the likelihood that one or more shorts may be formed between a bond wire and a pad and/or an adjacent bond wire. Increasing the number of bond pads tends to reduce the spacing between adjacent bond wires and to increase the likelihood of shorts. Further, bonding wires 104 connected between the more distant portions of the lead frame 102 and certain of the pads, e.g., pads 1, 8, 9 and 16, are substantially longer than those bonding wires connected between closer portions of the lead frame and other pads, e.g., pads 4, 5, 12 and 13. Different bonding wire lengths may result in a timing skew between the signals being transmitted through the bonding wires to the respective pads. These timing skews will tend to compromise signal integrity, disrupt high-speed operations and limit the rate at which the semiconductor device may be successfully operated.